This invention relates in general to pulse width modulation (PWM) techniques, and more particularly, to an automatically calibrated pulse width modulator.
In the past, pulse width modulation (PWM) techniques have been used in the context of control signal generation and also for electronic converters/inverters. Such converters/inverters employ square-wave switching wave forms wherein pulse width is varied in order to control load voltage. Such techniques have also been employed in the construction of integrated circuits (ICS) having pulse width modulators (PWMs).
One prior art technique for implementing an integrated circuit (IC) pulse width modulator (PWM) utilizes a design solution wherein the pulse width modulator (PWM) is run with a much higher clock frequency to generate the desired signal pulse widths and pulse justifications. The required clock frequency for a pulse width modulator (PWM) is proportional to the resolution, or granularity, of the pulse widths that can be generated. For example, where pulse widths ranging from 0 to 64 can be specified, in increments of {fraction (1/64)}th of the output period, such prior art solution technique would require a clock frequency that is 64 times the primary clock frequency. However, the resulting clock frequencies could be near 1 GHz, which is very difficult to implement in an integrated circuit (IC).
Another prior art technique for implementing an integrated circuit (IC) pulse width modulator (PWM) utilizes an analog voltage ramp circuit to calculate periods of time. The resulting circuit requires calibration of the ramp circuit to a desired frequency. A desired pulse width number, or value, is converted to a voltage value for the ramp reference voltage. The voltage value is proportional to the pulse width. A pulse is initiated when the voltage ramp begins, and ends when the ramp voltage reaches the reference voltage. Here, the reference voltage is generated from the pulse width input using a digital-to-analog converter (DAC). Such prior art design requires only the primary clock frequency to drive the control logic. However, such a design requires sensitive analog circuitry, which is not possible to implement in a digital-only integrated circuit (IC). Digital-only integrated circuits (ICS) tend to be the least expensive type of integrated circuit (IC) available. Hence, mixed analog and digital integrated circuits (ICS) are generally more expensive and more difficult to design.
Therefore, there exists a need for an improved pulse width modulator (PWM) that can be implemented on an integrated circuit (IC) in a manner that is more manageable, cost-effective and accurate than the prior art techniques.
Furthermore, there exists a need for a pulse width modulator (PWM) that can be implemented in an all-digital integrated circuit (IC). Such need exists for a design that is relatively small and east to implement, and that can be calibrated at any time without having to go into a special operating mode.
A reasonably accurate pulse width modulator is provided that is capable of being implemented in an all-digital integrated circuit (IC). Such modulator requires only a primary clock frequency, wherein the clock frequency is equal to the inverse of the pulse width modulator (PWM) output period. Such design proves relatively small and easy to implement. Additionally, the design includes a mechanism for doing self-calibration, which reduces the amount of system interaction and overhead. With this new modulator design, calibration needs to be performed since the modulator design relies on a delay-line technology in order to generate multiple, delayed clocks. These delay elements will not have a constant delay, but will vary with the specifics of the integrated circuit process, the operating temperature, and operating voltage changes. The self-calibration feature will allow delay settings to change, such that the delayed clocks will be proportional to the desired operating frequency. Additionally, this self-calibration process can be repeated often in order to compensate for sudden operating-condition changes.
According to one aspect of the invention, a pulse width modulator includes a clock operative to count successive discrete time intervals having a period equal to a desired full pulse width, and configured to generate a clock signal. The pulse width modulator also includes an adjustable delay line comprising a plurality of delay line elements, each delay line element operative to generate a clock signal at a specific location, which when combined with a transitional instruction, will produce a modulated output that has a plurality of transitions within the clock period. The pulse width modulator further includes processing circuitry configured to receive the clock signal and a pulse code input and operative to select one of the delay line elements to generate a clock signal at a specific location to produce a single modulated output that transitions at a desired modulated frequency.
According to another aspect of the invention, a printer is provided which includes a print engine having a pulse width modulator including a clock operative to count successive discrete time intervals having a period equal to a desired full pulse width, and configured to generate a clock signal, an adjustable delay line comprising a plurality of delay line elements, each delay line element operative to generate a clock signal at a specific location so as to generate a plurality of clocks, the plurality of clocks in cooperation with a transitional instruction, operative to produce a modulated output that has a plurality of transitions within the clock period, processing circuitry configured to receive the clock signal and a pulse code input and operative to select one of the delay line elements to generate a clock signal at a specific location so as to produce a single modulated output that transitions at a desired modulated frequency. The printer also includes an image-forming device configured to receive the single modulated output from the pulse width modulator and usable to generate a print image.
According to yet another aspect of the invention, a method of generating a pulse width modulated output is provided which includes an adjustable delay line operative to generate a plurality of adjustable delay line clocks to produce a modulated output that has a plurality of transitions within a clock period, delivers a system clock signal to the processing circuitry, and generates a transitional instruction that toggles the modulated output that is generated at a primary clock frequency.
One advantage of this invention is the resulting relatively smaller sized pulse width modulator (PWM) that can be produced on an all-digital integrated circuit (IC).
Another advantage of this invention is provided by the ability to calibrate delay cells to a desired frequency or anywhere within a broad range of frequencies, particularly the ability to calibrate multiple times during the printing of image data.
Yet another advantage of this invention is provided by the ability to frequently calibrate such delay cells to a desired frequency.
Yet even further advantages of this invention are provided wherein a self-calibration mechanism lends to more complete testing and verification of the integrated circuit (IC), thereby reducing unexpected failures. Additionally, the delay-line implementation of Applicant""s invention tends to provide a more accurate pulse width modulator (PWM) than was provided by previous delay-line technologies.